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| general description the max1415/max1416 low-power, 2-channel, serial- output analog-to-digital converters (adcs) use a sigma- delta modulator with a digital filter to achieve 16-bit resolution with no missing codes. these adcs are pin- compatible upgrades to the mx7705/ad7705. the max1415/max1416 feature an internal oscillator (1mhz or 2.4576mhz), an on-chip input buffer, and a program- mable gain amplifier (pga). the devices offer an spi -/ qspi -/microwire -compatible serial interface. the max1415 requires a single 2.7v to 3.6v supply, and the max1416 requires a single 4.75v to 5.25v supply. the operating supply current is 400? (max) with a 3v supply. power-down mode reduces the supply current to 2? (typ). when operating with a supply of 3v, the power dissipation is less than 1.44mw, making the max1415 ideal for battery-powered applications. self-calibration and system calibration allow the max1415/max1416 to correct for gain and offset errors. excellent dc performance (?.0015% fsr inl) and low noise (700nv in unbuffered mode) make the max1415/ max1416 ideal for measuring low-frequency signals with a wide dynamic range. these devices accept fully differ- ential bipolar/unipolar inputs. an internal input buffer allows for input signals with high source impedances. an on-chip digital filter, with a programmable cutoff and out- put data rate, processes the output of the sigma-delta modulator. the first notch frequency of the digital filter is chosen to provide 150db rejection of common-mode 50hz or 60hz noise and 98db rejection of normal-mode 50hz or 60hz noise. a pga and digital filtering allow sig- nals to be directly acquired with little or no signal-condi- tioning requirements. the max1415/max1416 are available in 16-pin pdip, so, and tssop packages. applications industrial instruments weigh scales strain-gauge measurements loop-powered systems flow and gas meters medical instrumentation pressure transducers thermocouple measurements rtd measurements features ? 16-bit sigma-delta adcs ? two fully differential input channels ? 0.0015% integral nonlinearity with no missing codes ? internal analog input buffers ? programmable gain amplifier (pga) from 1 to 128 ? internal oscillator (2.4576mhz or 1mhz) ? single 2.7v to 3.6v (max1415) or 4.75v to 5.25v (max1416) supply ? low power 1mw max, 3v supply 2? (typ) power-down current ? spi -/qspi -/microwire -com patible 3-wire serial interface ? pin compatible with mx7705/ad7705 ? 16-pin pdip, so, and tssop packages max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sclk gnd v dd din dout drdy ain2- ref- ref+ top view max1415 max1416 pdip/so/tssop clkin clkout ain2+ cs reset ain1+ ain1- pin configuration ordering information 19-3163; rev 1; 12/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package v dd ( v ) pkg code max1415 ene* -45? to +85? 16 pdip 3 p16-1 max1415ewe* -45? to +85? 16 wide so 3 w16-1 max1415eue -45? to +85? 16 tssop 3 u16-1 max1415aene* -45? to +85? 16 pdip 3 p16-1 max1415aewe* -45? to +85? 16 wide so 3 w16-1 max1415aeue* -45? to +85? 16 tssop 3 u16-1 max1415cne* 0? to +70? 16 pdip 3 p16-1 max1415cwe* 0? to +70? 16 wide so 3 w16-1 max1415cue* 0? to +70? 16 tssop 3 u16-1 spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. * future product? ontact factory for availability. ordering information continued at end of data sheet.
max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ax1415 (v dd = 3v, gnd = 0, v ref+ = 1.225v, v ref- = gnd, external f clkin = 2.4576mhz, clkdiv bit = 0, c ref+ to gnd = 0.1?, c ref- to gnd = 0.1?, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v all other pins to gnd.................................-0.3v to (v dd + 0.3v) maximum current input into any pin ..................................50ma continuous power dissipation (t a = +70 c) 16-pin pdip (derate 10.5mw/ c above +70 c)...........842mw 16-pin tssop (derate 9.4mw/ c above +70 c) .........755mw 16-pin wide so (derate 9.5mw/ c above +70 c) ......762mw operating temperature range ..........................-40 c to +85 c storage temperature range .............................-60 c to +150 c junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy resolution (no missing codes) 16 bits output noise (tables 1, 3) ? integral nonlinearity inl gain = 1, bipolar mode, unbuffered 0.0015 %fsr unipolar offset error after calibration (note 1) ? unipolar offset drift (note 2) 0.5 ?/? bipolar zero error after calibration (note 1) ? gain = 1 to 4 0.5 bipolar zero drift (note 2) gain = 8 to 128 0.1 ?/? positive full-scale error after calibration (notes 1, 3) ? full-scale drift (notes 2, 4) 0.5 ?/? gain error after calibration (notes 1, 5) ? gain drift (notes 2, 6) 0.5 ppm of fsr/? bipolar negative full-scale error after calibration 0.003 %fsr gain = 1 to 4 1 bipolar negative full-scale drift (note 2) gain = 8 to 128 0.6 ?/? analog inputs (ain1+, ain1-, ain2+, ain2-) unipolar input range 0 v ref / gain ain differential input voltage range (note 7) bipolar input range -v ref / gain v ref / gain v unbuffered gnd - 30mv v dd + 30mv ain absolute input voltage range (note 8) buffered gnd + 50mv v dd - 1.5v v ain dc leakage current unselected input channel 1 na max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs _______________________________________________________________________________________ 3 electrical characteristics?ax1415 (continued) (v dd = 3v, gnd = 0, v ref+ = 1.225v, v ref- = gnd, external f clkin = 2.4576mhz, clkdiv bit = 0, c ref+ to gnd = 0.1?, c ref- to gnd = 0.1?, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units gain = 1 34 gain = 2 38 gain = 4 45 ain input capacitance gain = 8 to 128 60 pf ain input sampling rate f s gain = 1 to 128 f clkin / 64 mhz gain = 1 105 gain = 2 110 gain = 4 120 input common-mode rejection cmr gain = 8 to 128 130 db normal-mode 50hz rejection for filter notches of 25hz, 50hz, 0.02 f notch 98 db normal-mode 60hz rejection for filter notches of 20hz, 60hz, 0.02 f notch 98 db common-mode 50hz rejection for filter notches of 25hz, 50hz, 0.02 f notch 150 db common-mode 60hz rejection for filter notches of 20hz, 60hz, 0.02 f notch 150 db external reference (ref+, ref-) ref differential input range v ref (note 9) 1.00 1.75 v ref absolute input voltage range gnd v dd v ref input capacitance gain = 1 to 128 10 pf ref input sampling rate f s f clkin / 64 mhz digital inputs (din, sclk, cs , reset ) input high voltage v ih 2.0 v input low voltage v il 0.4 v din, cs , reset 250 input hysteresis v hyst sclk 500 mv input current i in 1 a input capacitance 5pf clkin input clkin input high voltage v clkinh 2.5 v clkin input low voltage v clkinl 0.4 v clkin input current i clkin 10 ? digital outputs (dout, drdy , clkout) dout and drdy, i sink = 100? 0.4 output-voltage low v ol clkout, i sink = 10? 0.4 v max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 4 _______________________________________________________________________________________ electrical characteristics?ax1415 (continued) (v dd = 3v, gnd = 0, v ref+ = 1.225v, v ref- = gnd, external f clkin = 2.4576mhz, clkdiv bit = 0, c ref+ to gnd = 0.1?, c ref- to gnd = 0.1?, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units dout and drdy, i source = 100? v dd - 0.6v output-voltage high v oh clkout, i source = 10? v dd - 0.6v v tri-state leakage current i l dout only 10 ? tri-state output capacitance c out dout only 9 pf system calibration full-scale calibration range gain = selected pga gain (1 to 128) (note 10) -1.05 v ref / gain 1.05 v ref / gain v offset calibration range gain = selected pga gain (1 to 128) (note 10) -1.05 v ref / gain 1.05 v ref / gain v input span gain = selected pga gain (1 to 128) (notes 10, 11) 0.8 v ref / gain 2.1 v ref / gain v power requirements power-supply voltage v dd 2.7 3.6 v unbuffered, f clkin = 1mhz, gain = 1 to 128 0.40 buffered, f clkin = 1mhz, gain = 1 to 128 0.725 gain = 1 to 4 0.55 unbuffered, f clkin = 2.4576mhz gain = 8 to 128 0.55 gain = 1 to 4 0.825 buffered, f clkin = 2.4576mhz gain = 8 to 128 1.0 ma power-supply current (note 12) i dd power-down mode (note 13) 8 a power-supply rejection ratio psrr v dd = 2.7v to 3.6v (note 14) db external-clock timing specifications clkin frequency f clkin (note 15) 400 2500 khz duty cycle 40 60 % internal-clock timing specifications max1415ae__, f clk = 1mhz (clk = 0) or 2.4576mhz (clk = 1) t a = -40 c to +85 c ? max1415c__, f clk = 1mhz (clk = 0) or 2.4576mhz (clk = 1) t a = 0 c to +70? ? t a = -40 c to 0 c 7 internal-clock frequency f clk max1415e__, f clk = 1mhz (clk = 0) or 2.4576mhz (clk = 1) t a = 0 c to + 85 c ? % max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs _______________________________________________________________________________________ 5 electrical characteristics?ax1415 (continued) (v dd = 3v, gnd = 0, v ref+ = 1.225v, v ref- = gnd, external f clkin = 2.4576mhz, clkdiv bit = 0, c ref+ to gnd = 0.1?, c ref- to gnd = 0.1?, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units typical conversion-time variation ? t conv t conv = 1/odr ?.5 % electrical characteristics?ax1416 (v dd = 5v, gnd = 0, v ref+ = 2.5v, v ref- = gnd, f clkin = 2.4576mhz, clkdiv bit = 0, c ref+ to gnd = 0.1?, c ref- to gnd = 0.1?, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units dc accuracy resolution (no missing codes) 16 bits output noise (tables 1, 3) ? integral nonlinearity inl gain = 1, bipolar mode, unbuffered 0.0015 %fsr unipolar offset error after calibration (note 1) ? unipolar offset drift (note 2) 0.5 ?/? bipolar zero error after calibration (note 1) ? gain = 1 to 4 0.5 bipolar zero drift (note 2) gain = 8 to 128 0.1 ?/? timing characteristics?ax1415 (note 16) (figures 8, 9) parameter symbol conditions min typ max units drdy high time 500/ f clkin s reset pulse-width low 100 ns drdy fall to cs fall setup time t 1 0ns cs fall to sclk rise setup time t 2 120 ns sclk fall to dout valid delay t 3 0 100 ns sclk pulse-width high t 4 100 ns sclk pulse-width low t 5 100 ns cs rise to sclk rise hold time t 6 0ns bus relinquish time after sclk rising edge t 7 100 ns sclk fall to drdy rise delay t 8 100 ns din to sclk setup time t 9 30 ns din to sclk hold time t 10 20 ns max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 6 _______________________________________________________________________________________ electrical characteristics?ax1416 (continued) (v dd = 5v, gnd = 0, v ref+ = 2.5v, v ref- = gnd, f clkin = 2.4576mhz, clkdiv bit = 0, c ref+ to gnd = 0.1?, c ref- to gnd = 0.1?, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units positive full-scale error after calibration (notes 1, 3) ? full-scale drift (notes 2, 4) 0.5 ?/? gain error after calibration (notes 1, 5) ? gain drift (notes 2, 6) 0.5 ppm of fsr/? bipolar negative full-scale error after calibration 0.003 %fsr gain = 1 to 4 1 bipolar negative full-scale drift (note 2) gain = 8 to 128 0.6 ?/? analog inputs (ain1+, ain1-, ain2+, ain2-) unipolar input range 0 v ref / gain ain differential input voltage range (note 7) bipolar input range -v ref / gain v ref / gain v unbuffered gnd - 30mv v dd + 30mv ain absolute input voltage range (note 8) buffered gnd + 50mv v dd - 1.5v v ain dc leakage current unselected input channel 1 na gain = 1 34 gain = 2 38 gain = 4 45 ain input capacitance gain = 8 to 128 60 pf ain input sampling rate f s gain = 1 to 128 f clkin / 64 mhz gain = 1 96 gain = 2 105 gain = 4 110 input common-mode rejection cmr gain = 8 to 128 130 db normal-mode 50hz rejection for filter notches of 25hz, 50hz, 0.02 f notch 98 db normal-mode 60hz rejection for filter notches of 20hz, 60hz, 0.02 f notch 98 db common-mode 50hz rejection for filter notches of 25hz, 50hz, 0.02 f notch 150 db common-mode 60hz rejection for filter notches of 20hz, 60hz, 0.02 f notch 150 db max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs _______________________________________________________________________________________ 7 electrical characteristics?ax1416 (continued) (v dd = 5v, gnd = 0, v ref+ = 2.5v, v ref- = gnd, f clkin = 2.4576mhz, clkdiv bit = 0, c ref+ to gnd = 0.1?, c ref- to gnd = 0.1?, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units external reference (ref+, ref-) ref differential input range v ref (note 9) 1 3.5 v ref absolute input voltage gnd v dd v ref input capacitance gain = 1 to 128 10 pf ref input sampling rate f s f clkin / 64 mhz digital inputs (din, sclk, cs , reset ) input high voltage v ih 2v input low voltage v il 0.8 v din, cs , reset 250 input hysteresis v hyst sclk 500 mv input current i in 1 a input capacitance 5pf clkin input clkin input high voltage v clkinh 3.5 v clkin input low voltage v clkinl 0.8 v clkin input current i clkin 10 ? digital outputs (dout, drdy , clkout) dout and drdy, i sink = 800? 0.4 output-voltage low v ol clkout, i sink = 10? 0.4 v dout and drdy, i source = 200? 4.0 output-voltage high v oh clkout, i source = 10? 4.0 v tri-state leakage current i l dout only 10 ? tri-state output capacitance c out dout only 9 pf system calibration full-scale calibration range gain = selected pga gain (1 to 128) (note 10) -1.05 v ref / gain + 1.05 v re f / gain v offset calibration range gain = selected pga gain (1 to 128) (note 10) -1.05 v ref / gain + 1.05 v re f / gain v input span gain = selected pga gain (1 to 128) (notes 10, 11) 0.8 v ref / gain 2.1 v ref / gain v power requirements power-supply voltage v dd 4.75 5.25 v max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 8 _______________________________________________________________________________________ electrical characteristics?ax1416 (continued) (v dd = 5v, gnd = 0, v ref+ = 2.5v, v ref- = gnd, f clkin = 2.4576mhz, clkdiv bit = 0, c ref+ to gnd = 0.1?, c ref- to gnd = 0.1?, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units unbuffered, f clkin = 1mhz, gain = 1 to 128 0.45 buffered, f clkin = 1mhz, gain = 1 to 128 0.78 gain = 1 to 4 0.6 unbuffered, f clkin = 2.4576mhz gain = 8 to 128 0.6 gain = 1 to 4 0.95 buffered, f clkin = 2.4576mhz gain = 8 to 128 1.1 ma power-supply current (note 12) i dd power-down mode (note 13) 16 ? power-supply rejection ratio psrr v dd = 4.75v to 5.25v (note 14) db external-clock specifications clkin frequency f clkin (note 15) 400 2500 khz duty cycle 40 60 % internal-clock timing specifications max1416ae__, f clk = 1mhz (clk = 0) or 2.4576mhz (clk = 1) t a = -40 c to +85 c ? max1416c__, f clk = 1mhz (clk = 0) or 2.4576mhz (clk = 1) t a = 0 c to +70 c ? t a = -40 c to 0 c 7 internal-clock frequency f clk max1416e__, f clk = 1mhz (clk = 0) or 2.4576mhz (clk = 1) t a = 0 c to + 85 c ? % typical conversion-time variation ? t conv t conv = 1/odr, clk = 0 (1mhz), intclk = 1 ?.5 % timing characteristics?ax1416 (note 16) (figures 8, 9) parameter symbol conditions min typ max units drdy high time 500 / f clkin s reset pulse-width low 100 ns drdy fall to cs fall setup time t 1 0ns cs fall to sclk rise setup time t 2 120 ns sclk fall to dout valid delay t 3 080ns sclk pulse-width high t 4 100 ns sclk pulse-width low t 5 100 ns cs rise to sclk rise hold time t 6 0ns bus relinquish time after sclk rising edge t 7 60 ns sclk fall to drdy rise delay t 8 100 ns max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs _______________________________________________________________________________________ 9 note 1: these errors are in the order of the conversion noise shown in tables 1 and 3. this applies after calibration at the given temperature. note 2: recalibration at any temperature removes these drift errors. note 3: positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. note 4: full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipol ar input ranges. note 5: gain error does not include zero-scale errors. it is calculated as (full-scale error ?unipolar offset error) for unipolar rang es, and (full-scale error ?bipolar zero error) for bipolar ranges. note 6: gain-error drift does not include unipolar offset drift or bipolar zero drift. effectively, it is the drift of the part if only zero- scale calibrations are performed. note 7: the analog input voltage range on ain+ is given here with respect to the voltage on ain- on the max1415/max1416. note 8: this common-mode voltage range is allowed, provided that the input voltage on the analog inputs does not go more posi- tive than (v dd + 30mv) or more negative than (gnd - 30mv). parts are functional with voltages down to (gnd - 200mv), but with increased leakage at high temperature. note 9: the ref differential voltage, v ref , is the voltage on ref+ referenced to ref- (v ref = v ref+ - v ref-) . note 10: guaranteed by design. note 11: these calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed (v dd + 30mv) or go more negative than (gnd - 30mv). the offset-calibration limit applies to both the unipolar zero point and the bipolar zero point. note 12: when using a crystal or ceramic resonator across the clkin and clkout as the clock source for the device, the supply current and power dissipation varies depending on the crystal or resonator type. supply current is measured with the digi- tal inputs connected to 0 or v dd , clkin connected to an external clock source, and clkdis = 1. note 13: if the external master clock continues to run in power-down mode, the power-down current typically increases to 67? at 3v. when using a crystal or ceramic resonator across the clkin and clkout as the clock source for the device, the clock generator continues to run in power-down mode and the power dissipation depends on the crystal or resonator type (see the power-down modes section). note 14: measured at dc and applied in the selected passband. psrr at 50hz exceeds 120db with filter notches of 25hz or 50hz. psrr at 60hz exceeds 120db with filter notches of 20hz or 60hz. psrr depends on both gain and v dd . note 15: provide f clkin whenever the max1415/max1416 are not in power-down mode. if no clock is present, the device can draw higher-than-specified current and can possibly become uncalibrated. note 16: all input signals are specified with t r = t f = 5ns (10% to 90% of v dd ) and timed from a voltage level of 1.6v. gain psrr (v dd = 5v) psrr (v dd = 3v) (db) 19086 27878 48485 8 to 128 91 93 timing characteristics?ax1416 (continued) (note 16) (figures 8, 9) parameter symbol conditions min typ max units din to sclk setup time t 9 30 ns din to sclk hold time t 10 20 ns max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 10 ______________________________________________________________________________________ table 1. max1415?utput rms noise vs. gain and output data rate (3v) typical output rms noise (?) gain filter first notch and output data rate (hz) -3db frequency (hz) 1 2 4 8 16 32 64 128 buffered (f clkin = 1mhz) 20 5.24 2.85 1.63 2.16 0.70 0.67 0.63 0.64 0.62 25 6.55 3.46 1.92 1.13 6.05 0.75 0.73 0.70 0.70 100 26.2 48.94 26.98 11.99 0.85 3.44 2.27 1.66 1.72 200 52.4 270.91 161.33 66.19 32.64 16.89 8.34 4.98 4.86 unbuffered (f clkin = 1mhz) 20 5.24 3.09 1.70 1.05 0.72 0.66 0.64 0.60 0.60 25 6.55 3.58 1.94 1.23 0.80 0.77 0.73 0.70 0.70 100 26.2 51.92 24.54 11.47 6.14 3.26 2.16 1.67 1.64 200 52.4 263.86 136.78 65.40 34.51 16.64 8.97 4.96 4.80 buffered (f clkin = 2.4576mhz) 50 13.1 3.03 1.97 1.34 1.01 0.95 0.93 0.96 0.95 60 15.72 3.62 2.14 1.52 1.05 0.98 1.03 1.04 1.00 250 65.5 51.02 25.44 12.95 6.19 3.84 2.70 2.35 2.23 500 131 280.58 138.29 70.21 34.60 18.44 9.45 5.40 5.34 unbuffered (f clkin = 2.4576mhz) 50 13.1 3.76 1.63 0.96 0.69 0.66 0.64 0.59 0.61 60 15.72 3.11 1.86 1.12 0.78 0.75 0.71 0.71 0.69 250 65.5 48.28 25.13 12.75 6.18 3.32 2.12 1.59 1.62 500 131 280.67 143.15 75.84 34.70 17.88 9.19 4.90 4.98 max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 11 table 2. max1415?eak-to-peak resolution vs. gain and output data rate (3v) typical peak-to-peak resolution (bits) gain filter first notch and output data rate (hz) -3db frequency (hz) 1 2 4 8 16 32 64 128 buffered (f clkin = 1mhz) 20 5.24 16 16 16 16 15 14 13 12 25 6.55 16 16 16 12 15 14 13 12 100 26.2 12 12 12 16 12 12 11 11 200 52.4 10 10 10 10 10 10 10 9 unbuffered (f clkin = 1mhz) 20 5.24 16 16 16 16 15 14 13 12 25 6.55 16 16 16 16 15 14 13 12 100 26.2 12 12 12 12 12 12 12 11 200 52.4 10 10 10 10 10 10 10 9 buffered (f clkin = 2.4576mhz) 50 13.1 16 16 16 15 15 14 13 12 60 15.72 16 16 16 15 14 13 12 11 250 65.5 12 12 12 12 12 12 11 10 500 131 10 10 10 10 10 10 10 9 unbuffered (f clkin = 2.4576mhz) 50 13.1 16 16 16 16 15 14 13 12 60 15.72 16 16 16 16 15 14 13 12 250 65.5 12 12 12 12 12 12 12 11 500 131 10 10 10 10 10 10 10 9 max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 12 ______________________________________________________________________________________ table 3. max1416?utput rms noise vs. gain and output data rate (5v) typical output rms noise (?) gain filter first notch and output data rate (hz) -3db frequency (hz) 1248163264128 buffered (f clkin = 1mhz) 20 5.24 3.51 1.87 1.11 0.75 0.70 0.71 0.67 0.65 25 6.55 4.46 2.39 1.32 0.90 0.83 0.81 0.75 0.74 100 26.2 92.29 47.60 28.62 11.60 6.40 3.70 2.34 2.30 200 52.4 552.57 295.67 105.50 69.01 35.15 17.37 9.04 9.05 unbuffered (f clkin = 1mhz) 20 5.24 3.88 1.92 1.17 0.76 0.72 0.70 0.65 0.65 25 6.55 5.00 2.60 1.41 0.87 0.83 0.81 0.73 0.74 100 26.2 98.13 48.60 24.35 11.89 6.00 3.66 2.51 2.46 200 52.4 551.95 275.15 134.65 69.82 33.34 16.77 9.04 9.36 buffered (f clkin = 2.4576mhz) 50 13.1 4.10 2.56 1.68 1.23 1.19 1.21 1.15 1.19 60 15.72 4.52 2.96 1.89 1.32 1.32 1.27 1.28 1.31 250 65.5 96.62 47.35 26.33 12.42 7.10 4.30 3.16 3.19 500 131 568.80 292.49 151.10 71.96 36.61 19.18 9.95 10.23 unbuffered (f clkin = 2.4576mhz) 50 13.1 3.21 1.84 1.14 0.76 0.73 0.72 0.64 0.65 60 15.72 3.93 2.21 1.37 0.87 0.81 0.77 0.74 0.73 250 65.5 99.77 52.91 26.56 12.31 5.95 3.50 2.37 2.38 500 131 520.55 302.42 136.54 68.66 36.94 18.64 9.34 9.49 max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 13 table 4. max1416?eak-to-peak resolution vs. gain and output data rate (5v) typical peak-to-peak resolution (bits) gain filter first notch and output data rate (hz) -3db frequency (hz) 1 2 4 8 16 32 64 128 buffered (f clkin = 1mhz) 20 5.24 16 16 16 16 16 15 14 13 25 6.55 16 16 16 16 16 15 14 13 100 26.2 12 12 12 12 12 12 12 11 200 52.4 10 10 11 10 10 10 10 9 unbuffered (f clkin = 1mhz) 20 5.24 16 16 16 16 16 15 14 13 25 6.55 16 16 16 16 16 15 14 13 100 26.2 12 12 12 12 12 12 12 11 200 52.4 10 10 10 10 10 10 10 9 buffered (f clkin = 2.4576mhz) 50 13.1 16 16 16 16 15 14 13 12 60 15.72 16 16 16 16 15 14 13 12 250 65.5 12 12 12 12 12 12 12 10 500 131 10 10 10 10 10 10 10 9 unbuffered (f clkin = 2.4576mhz) 50 13.1 16 16 16 16 16 15 14 13 60 15.72 16 16 16 16 16 15 14 13 250 65.5 12 12 12 12 12 12 12 11 500 131 10 10 10 10 10 10 10 9 max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 14 ______________________________________________________________________________________ 5.15 5.05 4.95 4.85 -0.002 -0.001 0 0.001 0.002 0.003 -0.003 4.75 5.25 offset error vs. supply voltage (max1416) max1415/max1416 toc04 supply voltage (v) offset error (%fsr) 60 35 10 -15 -0.002 -0.001 0 0.001 0.002 0.003 -0.003 -40 85 offset error vs. temperature max1415/max1416 toc05 temperature ( c) offset error (%fsr) max1415 max1416 gain error vs. supply voltage (max1415) max1415/max1416 toc06 supply voltage (v) gain error (%fsr) 3.45 3.30 3.15 3.00 2.85 -0.0010 -0.0005 0 0.0005 0.0010 0.0015 -0.0015 2.70 3.60 gain error vs. supply voltage (max1416) max1415/max1416 toc07 supply voltage (v) gain error (%fsr) 5.15 5.05 4.95 4.85 -0.002 -0.001 0 0.001 0.002 0.003 -0.003 4.75 5.25 gain error vs. temperature max1415/max1416 toc08 temperature ( c) gain error (%fsr) 60 35 10 -15 -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0.004 0.005 -0.005 -40 85 max1415 max1416 typical output noise (max1416, buffered mode) max1415/max1416 toc01 reading number code read 1600 1200 800 400 32758 32760 32762 32764 32766 32768 32770 32772 32774 32776 32756 0 2000 v dd = 5v, v ref = 2.5v gain = 128 odr = 60hz rms noise = 1.3 v histogram of typical output noise (max1416, buffered mode) max1415/max1416 toc02 code occurrence 32773 32772 32771 32770 32769 32768 32767 32766 32765 32764 32763 32762 32761 100 200 300 400 0 32760 v dd = 5v, v ref = 2.5v gain = 128 odr = 60hz rms noise = 1.3 v offset error vs. supply voltage (max1415) max1415/max1416 toc03 supply voltage (v) offset error (%fsr) 3.45 3.30 3.15 3.00 2.85 -0.0010 -0.0005 0 0.0005 0.0010 0.0015 -0.0015 2.70 3.60 typical operating characteristics (max1415: v dd = 5v, v ref+ = 2.5v, v ref- = gnd, t a = +25?, unless otherwise noted.) (max1416: v dd = 3v, v ref+ = 1.225v, v ref- = gnd, t a = +25?, unless otherwise noted.) max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 15 supply current vs. supply voltage (max1415) max1415/max1416 toc09 supply voltage (v) supply current (ma) 3.45 3.30 3.15 3.00 2.85 0.3 0.4 0.5 a a: buffered mode f clkin = 2.4576mhz, gain = 8 to 128 b: buffered mode f clkin = 2.4576mhz, gain = 1 to 4 e: unbuffered mode f clkin = 1mhz, gain = 1 to 128 c: buffered mode f clkin = 1mhz, gain = 1 to 128 d: unbuffered mode f clkin = 2.4576mhz, gain = 1 to 128 b e d c 0.6 0.2 2.70 3.60 5.15 5.05 4.95 4.85 0.35 0.45 0.55 0.65 0.25 4.75 5.25 supply current vs. supply voltage (max1416) max1415/max1416 toc10 supply voltage (v) supply current (ma) a a: buffered mode f clkin = 2.4576mhz, gain = 8 to 128 b: buffered mode f clkin = 2.4576mhz, gain = 1 to 4 e: unbuffered mode f clkin = 1mhz, gain = 1 to 128 c: buffered mode f clkin = 1mhz, gain = 1 to 128 d: unbuffered mode f clkin = 2.4576mhz, gain = 1 to 128 b e d c 60 35 10 -15 0.3 0.4 0.5 0.6 0.2 -40 85 supply current vs. temperature (max1415) max1415/max1416 toc11 temperature ( c) supply current (ma) a a: buffered mode f clkin = 2.4576mhz, gain = 8 to 128 b: buffered mode f clkin = 2.4576mhz, gain = 1 to 4 e: unbuffered mode f clkin = 1mhz, gain = 1 to 128 c: buffered mode f clkin = 1mhz, gain = 1 to 128 d: unbuffered mode f clkin = 2.4576mhz, gain = 1 to 128 b e d c 60 35 10 -15 0.35 0.45 0.55 0.65 0.25 -40 85 supply current vs. temperature (max1416) max1415/max1416 toc12 temperature ( c) supply current (ma) a a: buffered mode f clkin = 2.4576mhz, gain = 8 to 128 b: buffered mode f clkin = 2.4576mhz, gain = 1 to 4 e: unbuffered mode f clkin = 1mhz, gain = 1 to 128 c: buffered mode f clkin = 1mhz, gain = 1 to 128 d: unbuffered mode f clkin = 2.4576mhz, gain = 1 to 128 b e d c typical operating characteristics (continued) (max1415: v dd = 5v, v ref+ = 2.5v, v ref- = gnd, t a = +25?, unless otherwise noted.) (max1416: v dd = 3v, v ref+ = 1.225v, v ref- = gnd, t a = +25?, unless otherwise noted.) max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 16 ______________________________________________________________________________________ supply current vs. f clkin (max1415) f clkin (mhz) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.6 0.3 0.4 0.5 0.6 0.2 max1415/max1416 toc13 supply current (ma) a a: buffered mode clk = 1, gain = 128 b: buffered mode clk = 1, gain = 1 e: unbuffered mode clk = 0, gain = 1, 128 c: buffered mode clk = 0, gain = 1, 128 d: unbuffered mode clk = 1, gain = 1, 128 b e d c supply current vs. f clkin (max1416) f clkin (mhz) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.6 0.35 0.45 0.55 0.65 0.25 max1415/max1416 toc14 supply current (ma) a a: buffered mode clk = 1, gain = 128 b: buffered mode clk = 1, gain = 1 e: unbuffered mode clk = 0, gain = 1, 128 c: buffered mode clk = 0, gain = 1, 128 d: unbuffered mode clk = 1, gain = 1, 128 b e d c gain 64 32 16 8 4 2 1 128 supply current vs. gain (max1415) 0.3 0.4 0.5 0.6 0.2 max1415/max1416 toc15 supply current (ma) a: buffered mode clk = 1, clkdiv = 1, f clkin = 4.9152mhz b: buffered mode clk = 1, clkdiv = 0, f clkin = 2.4576mhz e: unbuffered mode clk = 1, clkdiv = 0, f clkin = 2.4576mhz f: unbuffered mode clk = 0, clkdiv = 0, f clkin = 1mhz c: buffered mode clk = 0, clkdiv = 0, f clkin = 1mhz d: unbuffered mode clk = 1, clkdiv = 1, f clkin = 4.9152mhz f c a, b d, e gain 64 32 16 8 4 2 1128 supply current vs. gain (max1416) 0.35 0.45 0.55 0.65 0.25 max1415/max1416 toc16 supply current (ma) a a: buffered mode clk = 1, clkdiv = 1, f clkin = 4.9152mhz b: buffered mode clk = 1, clkdiv = 0, f clkin = 2.4576mhz e: unbuffered mode clk = 1, clkdiv = 0, f clkin = 2.4576mhz f: unbuffered mode clk = 0, clkdiv = 0, f clkin = 1mhz c: buffered mode clk = 0, clkdiv = 0, f clkin = 1mhz d: unbuffered mode clk = 1, clkdiv = 1, f clkin = 4.9152mhz b e f d c typical operating characteristics (continued) (max1415: v dd = 5v, v ref+ = 2.5v, v ref- = gnd, t a = +25?, unless otherwise noted.) (max1416: v dd = 3v, v ref+ = 1.225v, v ref- = gnd, t a = +25?, unless otherwise noted.) max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 17 power-down supply current vs. supply voltage (max1415) supply voltage (v) power-down supply current (na) 3.45 3.30 3.15 3.00 2.85 20 40 60 80 100 0 2.70 3.60 max1415/max1416 toc17 5.15 5.05 4.95 4.85 120 140 160 180 200 100 4.75 5.25 power-down supply current vs. supply voltage (max1416) supply voltage (v) power-down supply current (na) max1415/max1416 toc18 power-down supply current vs. temperature max1415/max1416 toc19 temperature ( c) power-down supply current (na) 60 35 10 -15 50 100 150 200 250 300 0 -40 85 max1415 v dd = 5v max1416 v dd = 3v external oscillator startup time 2ms/div v dd 5v/div clkout 5v/div clkout 5v/div max1415/max1416 toc20 4.9152mhz crystal 2.4576mhz crystal internal oscillator startup time 4 s/div sclk 5v/div clkout 5v/div clk = 1 clkout 5v/div clk = 0 max1415/max1416 toc21 16th rising edge of sclk typical operating characteristics (continued) (max1415: v dd = 5v, v ref+ = 2.5v, v ref- = gnd, t a = +25?, unless otherwise noted.) (max1416: v dd = 3v, v ref+ = 1.225v, v ref- = gnd, t a = +25?, unless otherwise noted.) max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 18 ______________________________________________________________________________________ pin description pin name function 1 sclk serial clock input. apply an external serial clock to transfer data to and from the device at data rates up to 5mhz. 2 clkin clock input. connect a crystal/resonator between clkin and clkout, or drive clkin externally with a cmos-compatible clock source. connect clkin to gnd when using the internal oscillator. 3 clkout clock output. connect a crystal/resonator between clkin and clkout. when enabled, clkout provides a cmos-compatible, inverted clock output. clkout can drive one cmos load. set clkdis = 0 in the clock register to enable clkout. set clkdis = 1 in the clock register to disable clkout. 4 cs active-low chip-select input. cs selects the active device in systems with more than one device on the serial bus. drive cs low to clock data in on din and to clock data out on dout. when cs is high, dout is high impedance. connect cs to gnd for 3-wire operation. 5 reset active-low reset input. drive reset low to reset the max1415/max1416 to power-on reset status. 6 ain2+ channel 2 positive analog input 7 ain1+ channel 1 positive analog input 8 ain1- channel 1 negative analog input 9 ref+ positive reference input 10 ref- negative reference input 11 ain2- channel 2 negative analog input 12 drdy active-low data ready output. drdy goes low when a new conversion result is available in the data register. when a read operation of a full output word completes, drdy returns high. 13 dout serial data output. dout outputs serial data from the data register. dout changes on the falling edge of sclk and is valid on the rising edge of sclk. when cs is high, dout is high impedance. 14 din serial data input. data on din is clocked in on the rising edge of sclk when cs is low. 15 v dd power input. connect v dd to a 2.7v to 3.6v power supply for the max1415, and connect v dd to a 4.75v to 5.25v power supply for the max1416. 16 gnd ground detailed description the max1415/max1416 low-power, 2-channel serial output adcs use a sigma-delta modulator with a digital filter to achieve 16-bit resolution with no missing codes. each device includes a pga, an on-chip input buffer, an internal oscillator, and a bidirectional communica- tions port. the max1415 operates with a 2.7v to 3.6v single supply, and the max1416 operates with a 4.75v to 5.25v single supply. fully differential inputs, an internal input buffer, and an on-chip pga (gain = 1 to 128) allow low-level signals to be directly measured, minimizing the requirements for external signal conditioning. self-calibration corrects for gain and offset errors. a programmable digital filter allows for the selection of the output data rate and first notch frequency from 20hz to 500hz. the bidirectional serial spi-/qspi-/microwire-compati- ble interface consists of four digital control lines (sclk, cs , dout, and din) and provides an easy interface to microcontrollers (?s). connect cs to gnd to configure the max1415/max1416 for 3-wire operation. analog inputs the max1415/max1416 accept four analog inputs (ain1+, ain1-, ain2+, and ain2-) in buffered or unbuffered mode. use table 8 to select the positive and negative input pair for a fully differential channel. the input buffer isolates the inputs from the capacitive load presented by the pga/modulator, allowing for high source-impedance analog transducers. the value of the buf bit in the setup register (see the setup register section) determines whether the input buffer is enabled or disabled. internal protection diodes, which clamp the analog input to v dd and/or gnd, allow the input to swing from (gnd - 0.3v) to (v dd + 0.3v), without damaging the device. if the analog input exceeds 300mv beyond the supplies, limit the input current to 10ma. input buffers when the analog input buffer is disabled, the analog input drives a typical 7pf (gain = 1) capacitor, c total , in series with the 7k ? typical on-resistance of the track and hold (t/h) switch (figure 1). c total is comprised of the sampling capacitor, c samp , and the stray capac- itance, c stray . during the conversion, c samp charges to (ain+ - ain-). the gain determines the value of c samp (see table 5). max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 19 max1415 max1416 mux clock generator digital filter 2nd-order sigma-delta modulator pga buffer buffer serial interface, registers, and control v dd gnd sclk din dout clkin clkout ain1+ ain1- ain2+ ain2- ref+ ref- s1 s2 s1 and s2 are open in buffered mode and closed in unbuffered mode cs drdy reset functional diagram max1415/max1416 to minimize gain errors in unbuffered mode, select a source impedance less than the maximum values shown in figures 2 and 3. these are the maximum external resistance/capacitance combinations allowed before gain errors greater than 1 lsb are introduced in unbuffered mode. enable the internal input buffer for a high source imped- ance. this isolates the inputs from the sampling capaci- tor and reduces the sampling-related gain error. when using the internal buffer, limit the absolute input voltage range to (v gnd + 50mv) to (v dd - 1.5v). properly set up the gain and common-mode voltage range to mini- mize linearity errors. input voltage range in unbuffered mode, the absolute analog input voltage range is from (gnd - 30mv) to (v dd + 30mv) (see the electrical characteristics section). in buffered mode, the analog input voltage range is reduced to (gnd + 50mv) to (v dd - 1.5v). in both buffered and unbuffered modes, the differential analog input range (v ain+ - v ain- ) decreases at higher gains (see the programmable gain amplifier and unipolar and bipolar modes sections). reference the max1415/max1416 provide differential inputs, ref+ and ref-, for an external reference voltage. connect the external reference directly across ref+ and ref- to obtain the differential reference voltage, v ref . the common-mode voltage range for v ref+ and v ref- is between gnd and v dd . for specified operation, the nominal voltage, v ref is 1.225v for the max1415 and 2.5v for the max1416. the max1415/max1416 sample ref+ and ref- at f clkin /64 (clkdiv = 0) or f clkin /128 (clkdiv = 1) with an internal 10pf (typ for gain = 1) sampling capac- itor in series with a 7k ? (typ) switch on-resistance. programmable gain amplifier a pga provides selectable levels of gain: 1, 2, 4, 8, 16, 32, 64, and 128. bits g0, g1, and g2 in the setup reg- ister control the gain (see table 9). as the gain increas- es, the value of the input sampling capacitor, c samp , also increases (see table 5). the dynamic load pre- sented to the analog inputs increases with clock fre- quency and gain in unbuffered mode (see the input buffers section and figure 1). 16-bit, low-power, 2-channel, sigma-delta adcs 20 ______________________________________________________________________________________ high- impedance input r sw (7k ? typ) c total (7pf typ for gain = 1) ain(+) ain(-) v bias c total = c samp + c stray figure 1. unbuffered analog input structure maximum external resistance vs. maximum external capacitance (1mhz) 0.1 1 10 100 1 10 100 1000 10,000 external capacitance (pf) external resistance (k ? ) gain = 1 gain = 2 gain = 4 gain = 8 to 128 figure 2. maximum external resistance vs. maximum external capacitance for unbuffered mode (1mhz) maximum external resistance vs. maximum external capacitance (2.4576mhz) 0.1 1 10 100 1 10 100 1000 10,000 external capacitance (pf) external resistance (k ? ) gain = 2 gain = 4 gain = 8 to 128 gain = 1 figure 3. maximum external resistance vs. maximum external capacitance for unbuffered mode (2.4576mhz) increasing the gain increases the resolution of the adc (lsb size decreases), but reduces the differential input voltage range. calculate 1 lsb in unipolar mode using the following equation: where: v ref = v ref+ - v ref-. for a gain of 1 and v ref = 2.5v, the full-scale voltage in unipolar mode is 2.5v and 1 lsb 38.1?. for a gain of 4, the full-scale voltage in unipolar mode is 0.625v (v ref /gain) and 1 lsb 9.5?. the differential input voltage range in this example reduces from 2.5v to 0.625v, and the resolution increases since the lsb size decreases from 38.1? to 9.5?. calculate 1 lsb in bipolar mode using the following equation: where: v ref = v ref+ - v ref-. unipolar and bipolar modes the b /u bit in the setup register ( table 9) configures the max1415/max1416 for unipolar or bipolar transfer functions. figures 4 and 5 illustrate the unipolar and bipolar transfer functions, respectively. in unipolar mode, the digital output code is straight binary. when ain+ = ain-, the outputs are at zero scale, which is the lower endpoint of the transfer func- tion. the full-scale endpoint is given by ain+ - ain- = v ref / gain, where v ref = v ref+ - v ref- . in bipolar mode, the digital output code is in offset binary. positive full scale is given by ain+ - ain- = +v ref / gain and negative full scale is given by ain+ - ain- = -v ref / gain. when ain+ = ain-, the outputs are at zero scale, which is the midpoint of the bipolar transfer function. when the max1415/max1416 are in buffered mode, the absolute and common-mode analog input voltage ranges reduce to between (gnd + 50mv) and (v dd - 1.5v). the differential input voltage range is not affected in buffered mode. 1 65 536 2 (, ) lsb v gain ref = 1 65 536 (, ) lsb v gain ref = max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 21 table 5. input sampling capacitor vs. gain gain input sampling capacitor (c samp ) (pf) 1 3.75 2 7.5 415 8?28 30 0123 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0011 full-scale transition 1 lsb = v ref (gain) (65,536) 65,535 65,533 differential input voltage (lsb) 1111 1111 1111 1101 1111 1111 1111 1110 1111 1111 1111 1111 1111 1111 1111 1100 v ref /gain v ref /gain binary output code figure 4. max1415/max1416 unipolar transfer function 1 lsb = v ref (gain) (65,536) 0+1 -1 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0010 +32,767 binary output code +32,765 1111 1111 1111 1101 1111 1111 1111 1110 1111 1111 1111 1111 1000 0000 0000 0000 1000 0000 0000 0001 0111 1111 1111 1111 x 2 -32,768 -32,766 differential input voltage (lsb) v ref /gain v ref /gain v ref /gain v ref /gain figure 5. max1415/max1416 bipolar transfer function max1415/max1416 modulator the max1415/max1416 perform analog-to-digital con- versions using a single-bit, 2nd-order, switched-capac- itor, sigma-delta modulator. the sigma-delta modulator converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal infor- mation. a single comparator within the modulator quan- tizes the input signal at a much higher sample rate than the bandwidth of the input. the max1415/max1416 modulator provides 2nd-order frequency shaping of the quantization noise resulting from the single-bit quantizer. the modulator is fully dif- ferential for maximum signal-to-noise ratio and mini- mum susceptibility to power-supply and common-mode noise. a single-bit data stream is then presented to the digital filter for processing to remove the frequency- shaped quantization noise. the modulator sampling frequency is f clkin / 128, regardless of gain, where f clkin (clkdiv = 0) is the frequency of the signal at clkin. digital filtering the max1415/max1416 contain an on-chip, digital low- pass filter that processes the 1-bit data stream from the modulator using a sinc 3 (sinx/x) 3 response. the sinc 3 filter has a settling time of three output data periods. filter characteristics figure 6 shows the filter frequency response. the sinc 3 characteristic -3db cutoff frequency is 0.262 times the first notch frequency. this results in a cutoff frequency of 15.72hz for a first filter notch frequency of 60hz (output data rate of 60hz). the response shown in figure 5 is repeated at either side of the digital filter? sample frequency, f m (f m = 19.2khz for 60hz output data rate), and at either side of the related harmonics (2f m , 3f m , and so on). the output data rate for the digital filter corresponds with the positioning of the first notch of the filter? frequency response. therefore, for the plot in figure 6, where the first notch of the filter is 60hz, the output data rate is 60hz. the notches of the sinc 3 filter are repeated at multiples of the first notch frequency. the sinc 3 filter provides an attenua- tion of better than 100db at these notches. determine the cutoff frequency of the digital filter by load- ing the appropriate values into the clk, fs0, and fs1 bits in the clock register (see table 13). programming a different cutoff frequency with fs0 and fs1 changes the frequency of the notches, but it does not alter the profile of the frequency response. for step changes at the input, allow a settling time before valid data is read. the settling time depends on the output data rate chosen for the filter. the worst- case settling time of a sinc 3 filter for a full-scale step input is four times the output data period. by synchro- nizing the step input using fsync, the settling time reduces to three times the output data period. if fsync is high during the step input, the filter settles in three times the data output period after fsync falls low. analog filtering the digital filter does not provide any rejection close to the harmonics of the modulator sample frequency. due to the high oversampling ratio of the max1415/max1416, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. the analog filtering requirements in front of the max1415/max1416 are reduced compared to a conventional converter with no on-chip filtering. in addition, the devices provide excellent common-mode rejection to reduce the common-mode noise susceptibility. additional filtering prior to the max1415/max1416 elim- inates unwanted frequencies the digital filter does not reject. use additional filtering to ensure that differential noise signals outside the frequency band of interest do not saturate the analog modulator. if passive components are in the path of the analog inputs when the device is in unbuffered mode, ensure the source impedance is low enough (figure 2) not to introduce gain errors in the system. this significantly limits the amount of passive anti-aliasing filtering that can be applied in front of the max1415/max1416 in unbuffered mode. in buffered mode, large source impedance causes a small dc-offset error, which can be removed by calibration. 16-bit, low-power, 2-channel, sigma-delta adcs 22 ______________________________________________________________________________________ -160 -120 -140 -100 -80 -60 -20 -40 0 0 406080 20 100 120 140 160 180 200 frequency (hz) gain (db) f clkin = 2.4576mhz clk = 1 fs1 = 0 fs0 = 1 f n = 60hz figure 6. frequency response of the sinc 3 filter (notch at 60hz) internal oscillator mode in internal oscillator mode (intclk = 1), set the clk bit in the clock register ( table 12) to 0 to operate at a clock frequency of 1mhz, or set clk to 1 for a frequency of 2.4576mhz. the clkdiv bit is not used in this mode. internal-clock startup time the internal clock requires time to stabilize during power-on reset. this startup time is dependent on the internal-clock frequency (see the typical operating characteristics section). the typical startup time for the internal oscillator is less than 35?, while the external oscillator startup time when using a crystal or resonator is in the order of milliseconds. external oscillator the oscillator requires time to stabilize when enabled. startup time for the oscillator depends on supply voltage, temperature, load capacitances, and center frequency. depending on the load capacitance, a 1m ? feedback resistor across the crystal can reduce the startup time (figure 7). the max1415/max1416 were tested with an ecs-24-32-1 (2.4576mhz crystal) and an ecs-49-20-1 (4.9152mhz crystal) (see the typical operating char- acteristics section). when the external oscillator is enabled, the supply current is typically 67? with a 3v supply and 227? with a 5v supply. serial digital interface the max1415/max1416 interface is fully compatible with spi-, qspi-, and microwire-standard serial interfaces. the serial interface provides access to seven on-chip registers. the registers are 8, 16, and 24 bits in size. drive cs low to transfer data in and out of the max1415/max1416. clock in data at din on the rising edge of sclk. data at dout changes on the falling edge of sclk and is valid on the rising edge of sclk. din and dout are transferred msb first. drive cs high to force dout high impedance and cause the max1415/max1416 to ignore any signals on sclk and din. connect cs low for 3-wire operation. figures 8 and 9 show the timings for write and read operations, respectively. on-chip registers the max1415/max1416 contain seven internal registers (figure 10), which are accessed by the serial interface. these registers control the various functions of the device and allow the results to be read. table 7 lists the address, power-on default value, and size of each register. the first of these registers is the communications register. the 8-bit communications register controls the acquisi- tion-channel selection, whether the next data transfer is a read or write operation, and which register is to be accessed. the second register is the 8-bit setup register, which controls calibration modes, gain setting, unipolar/bipolar inputs, and buffered/unbuffered modes. the third register is the 8-bit clock register, which sets the digital filter characteristics and the clock control bits. the fourth register is the 16-bit data register, which holds the output result. the 24-bit offset and gain registers store the calibration coefficients for the max1415/max1416. the 8- bit test register is used for factory testing only. max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 23 crystal or ceramic resonator c l c l clkin clkout optional 1m ? max1415 max1416 figure 7. using a crystal or ceramic oscillator cs t 2 t 6 t 9 t 10 sclk msb lsb din figure 8. write timing diagram t 2 t 4 t 5 t 3 t 8 t 6 t 7 t 1 sclk msb lsb dout cs drdy figure 9. read timing diagram max1415/max1416 the default state of the max1415/max1416 is to wait for a write to the communications register. any write or read operation on the max1415/max1416 is a two-step process. first, a command byte is written to the com- munications register. this command selects the input channel, the desired register for the next read or write operation, and whether the next operation is a read or a write. the second step is to read from or write to the selected register. at the end of the data-transfer cycle, the device returns to the default state. see the performing a conversion section for examples. if the serial communication is lost, write 32 ones to the ser- ial interface to return the max1415/max1416 to the default state. the registers are not reset after this operation. communications register the byte-wide communications register is bidirectional so it can be written and read. the byte written to the communications register indicates the next read or write operation on the selected register, the power-down mode, and the analog input channel (see table 6). the drdy bit indicates the conversion status. 0/ drdy : (default = 0) communication-start/data-ready bit. write a 0 to the 0/ drdy bit to start a write operation to the communications register. if 0/ drdy = 1, then the device waits until a 0 is written to 0/ drdy before continu- ing to load the remaining bits. for a read operation, the 0/ drdy bit shows the status of the conversion. the drdy bit returns a 0 if the conversion is complete and the data is ready. drdy returns a 1 if the new data has been read and the next conversion is not yet complete. it has the same value as the drdy output pin. rs2, rs1, rs0: (default = 0, 0, 0) register-select bits. rs2, rs1, and rs0 select the next register to be accessed as shown in table 7. r/ w : (default = 0) read-/write-select bit. use this bit to select if the next register access is a read or a write operation. set r/ w = 0 to select a write operation, or set r/ w = 1 for a read operation on the selected register. pd: (default = 0) power-down control bit. set pd = 1 to initiate power-down mode. set pd = 0 to take the device out of power-down mode. if the internal oscilla- tor or external crystal/resonator is used and clkdis = 0, clkout remains active during power-down mode to provide a clock source for other devices in the system. ch1, ch0: (default = 0, 0) channel-select bit. write to the ch1 and ch0 bits to select the conversion channel or to access the calibration data shown in table 8. the cali- bration coefficients of a particular channel are stored in one of the three offset and gain register pairs in table 8. set ch1 = 1 and ch0 = 0 to evaluate the noise perfor- mance of the part without external noise sources. in this noise-evaluation mode, connect ain1- to an external volt- age within the allowable common-mode range. setup register the byte-wide setup register is bidirectional so it can be written and read. the byte written to the setup regis- ter sets the calibration modes, pga gain, unipolar/bipo- lar mode, buffer enable, and conversion start (see table 9). md1, md0: (default = 0, 0) mode-select bits. see table 10 for normal operating mode, self-calibration, zero-scale calibration, or full-scale calibration-mode selection. 16-bit, low-power, 2-channel, sigma-delta adcs 24 ______________________________________________________________________________________ setup register (8 bits) rs2 rs1 rs0 clock register (8 bits) data register (16 bits) test register (8 bits)* offset register (24 bits) gain register (24 bits) communications register register select decoder din dout *the test register is used for factory testing only. figure 10. register summary g2, g1, g0: (default = 0, 0, 0) gain-selection bits. see table 11 for pga gain settings. b /u: (default = 0) bipolar-/unipolar-mode selection: set b /u = 0 to select bipolar mode. set b /u = 1 to select unipolar mode. buf: (default = 0) buffer-enable bit. for unbuffered mode, disable the internal buffer of the max1415/ max1416 to reduce power consumption by writing a 0 to the buf bit. write a 1 to this bit to enable the buffer. use the internal buffer when acquiring high source-imped- ance input signals. fsync: (default = 1) filter-synchronization/ conversion-start bit. set fsync = 0 to begin calibration or conversion. the max1415/max1416 perform free-run- ning conversions while fsync = 0. set fsync = 1 to stop converting data and to hold the nodes of the digital filter, the filter-control logic, the calibration-control logic, and the analog modulator in a reset state. the drdy output does not reset high if it is low (indicating that valid data has not yet been read from the data register) when fsync goes high. to clear drdy output, read the data register. max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 25 table 6. communications register (msb) (lsb) function communication start/data ready register select read/write select power-down mode channel select name 0/ drdy rs2 rs1 rs0 r/ w pd ch1 ch0 defaults 0 0 0 0 0 0 0 0 table 7. register selection rs2 rs1 rs0 register power-on reset status register size (bits) 0 0 0 communications register 0x00 8 0 0 1 setup register 0x01 8 0 1 0 clock register 0x85 8 0 1 1 data register n/a 16 1 0 0 test register* n/a 8 1 0 1 no operation 1 1 0 offset register 0x1f 40 00 24 1 1 1 gain register 0x57 61 ab 24 table 8. channel selection ch1 ch0 ain+ ain- offset/gain register pair 0 0 ain1+ ain1- 0 0 1 ain2+ ain2- 1 1 0 ain1- ain1- 0 1 1 ain1- ain2- 2 * the test register is used for factory testing only. table 9. setup register (msb) (lsb) function mode control pga gain control bipolar/unipolar mode buffer enable fsync name md1 md0 g2 g1 g0 b /u buf fsync defaults 0 0 0 0 0 0 0 1 max1415/max1416 clock register the byte-wide clock register is bidirectional, so it can be written and read. the byte written to the setup regis- ter sets the clock, filter first notch frequency, and the output data rate (see table 12). mxid: (default = 1) maxim-identifier bit. this is a read- only bit. values written to this bit are ignored. zero: (default = 0) zero bit. this is a read-only bit. values written to this bit are ignored. intclk: (default = 0) internal oscillator bit. set intclk = 1 to enable the internal oscillator. set intclk = 0 to disable the internal oscillator. clkdis: (default = 0) clock-disable bit. set clkdis = 1 to disable the internally or externally generated clock from appearing on clkout. when using a crystal or res- onator across clkin and clkout, the clock is stopped and no conversions take place when clkdis = 1. clkout is held low during clock disable to save power. set clkdis = 0 to allow other devices to use the output signal on clkout as a clock source and/or to enable the external oscillator. the clkout pin on the max1415/ max1416 can drive one cmos load. clkdiv: (default = 0) clock-divider control bit. the max1415/max1416 each have an internal clock divider. set this bit to 1 to divide the input clock by two. when this bit is set to 0, the max1415/max1416 operate at the internal or external oscillator frequency. clkdiv has no effect on the internal oscillator. clk: (default = 1) clock bit. when using the internal oscillator (intclk = 1), set clk = 1 for a frequency of 2.4576mhz, and set clk = 0 for a frequency of 1mhz. when using an external clock/oscillator, set clk = 1 for f clkin = 2.4576mhz with clkdiv = 0, or f clkin = 4.9152mhz with clkdiv = 1. 16-bit, low-power, 2-channel, sigma-delta adcs 26 ______________________________________________________________________________________ table 10. operating-mode selection md1 md0 operating mode 0 0 normal mode. use this mode to perform normal conversions on the selected analog input channel. 01 self-calibration mode. this mode performs self-calibration on the selected channel determined from ch0 and ch1 selection bits in the communications register (table 6). upon completion of self-calibration, the device returns to normal mode with md1, md0 returning to 0, 0. the drdy output bit goes high when self-calibration is requested and returns low when the calibration is complete and a new data word is in the data register. self- calibration performs an internal zero-scale and full-scale calibration. the analog inputs of the device are shorted together internally during zero-scale calibration and connected to an internally generated (v ref /gain) voltage during full-scale calibration. the offset and gain registers for the selected channel are automatically updated with the calibration data. 10 zero-scale system-calibration mode. this mode performs zero-scale calibration on the selected channel determined from ch1 and ch0 selection bits in the communications register (table 6). the drdy output bit goes high when calibration is requested and returns low when the calibration is complete and a new data word is in the data register. performing zero-scale calibration compensates for any dc offset voltage present in the adc and system. ensure that the analog input voltage is stable within 0.5 lsb for the duration of the calibration sequence. the offset register for the selected channel is updated with the zero-scale system-calibration data. upon completion of calibration, the device returns to normal mode with md1, md0 returning to 0, 0. 11 full-scale system-calibration mode. this mode performs full-scale system-calibration on the selected channel determined from ch1 and ch0 selection bits in the communications register. this calibration assigns a full- scale output code to the voltage present on the selected channel. ensure that the analog input voltage is stable within 0.5 lsb for the duration of the calibration sequence. the drdy output bit goes high during calibration and returns low when the calibration is complete and a new data word is in the data register. the gain register for the selected channel is updated with the full-scale system-calibration data. upon completion of calibration, the device returns to normal mode with md1, md0 returning to 0, 0. table 11. pga gain selection g2 g1 g0 pga gain 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 set clk = 0 if the external clock frequency is 1mhz with clkdiv = 0 or 2mhz with clkdiv = 1. fs1, fs0: (default = 0, 1) filter-selection bits. these bits, in addition to the clk bit, determine the output data rate and the digital filter cutoff frequency. see table 13 for fs1 and fs0 settings. recalibrate when the filter charac- teristics are changed. data register the data register is a 16-bit read-only register. figure 9 shows how to read conversion results using the data register. the data from the data register is read through dout. dout changes on the falling edge of sclk and is valid on the rising edge of sclk. the data-register format is 16-bit straight binary for unipolar mode with zero scale equal to 0x0000, and offset binary for bipolar mode with zero scale equal to 0x1000. test register this register is reserved for factory testing of the device. for proper operation of the max1415/ max1416, do not change this register from its default power-on reset values. offset and gain-calibration registers the max1415/max1416 contain one offset register and one gain register for each input channel. each register is 24 bits wide and can be written and read. the offset registers store the calibration coefficients resulting from a zero-scale calibration, and the gain registers store the calibration coefficients resulting from a full-scale calibration. the data stored in these registers are 24-bit straight binary values representing the offset or gain errors associated with the selected channel. a 24-bit read or write operation can be performed on the cali- bration registers for any selected channel. during a write operation, 24 bits of data must be written to the register, or no data is transferred. max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 27 table 13. output data rate and notch frequency vs. filter select and clkin frequency clkin frequency f clkin (mhz)* clk fs1 fs0 output data rate (first notch) (hz) -3db filter cutoff** (hz) 1 0 0 0 20 5.24 1 0 0 1 25 6.55 1 0 1 0 100 26.2 1 0 1 1 200 52.4 2.4576 1 0 0 50 13.1 2.4576 1 0 1 60 15.7 2.4576 1 1 0 250 65.5 2.4576 1 1 1 500 131 * these values are given for clkdiv = 0. external-clock frequency, f clkin , equals two times the values in this column if clkdiv = 1. ** the filter -3db filter cutoff frequency = 0.262 x filter first notch frequency. table 12. clock register (msb) (lsb) function reserved internal clock enable clock disable clock divider clock select filter select name mxid zero intclk clkdis clkdiv clk fs1 fs0 defaults 1 0 0 0 0 1 0 1 max1415/max1416 write to the calibration registers in normal mode only. after writing to the calibration registers, the devices implement the new offset and gain-register calibration coefficients at the beginning of a new acquisition. to ensure the results are valid, discard the first conversion result after writing to the calibration registers. to ensure that a conversion is not made using invalid calibration data, drive fsync high prior to writing to the calibration registers, and then release fsync low to ini- tiate conversion. power-on reset at power-up, the serial interface, logic, digital filter, and modulator circuits are reset. the registers are set to their default values. the device returns to wait for a write to the communications register. for accurate measure- ments, perform calibration routines after power-up. allow time for the external reference and internal or external oscillator to start up before starting calibration. see the typical operating characteristics for typical internal and external oscillator startup times. reset drive reset low to reset the max1415/max1416 to power-on reset status. drdy goes high and all communi- cation to the max1415/max1416 is ignored while reset is low. upon releasing reset , the device must be recon- figured to begin a conversion. the device returns to wait- ing for a write to the communication register after a reset has been performed. perform a calibration sequence fol- lowing a reset for accurate conversions. when using an external clock or crystal oscillator, the max1415/max1416 clock generator continues to run when reset is pulled low. this allows any device run- ning from clkout to be uninterrupted when the device is in reset while using an external clock. selecting custom output data rates and first notch frequency the recommended frequency range of the external clock is 400khz to 2.5mhz (clkdw = 0). the output data rate and first notch frequency are dependent on the decimation rate of the digital filter. table 14 shows the available decimation rates of the digital filter. the out- put data rate and filter first notch is calculated using the following formula: (if clkdiv = 1). (if clkdiv = 0). note: first notch filter frequency = output data rate. performing a conversion at power-on reset, the max1415/max1416 expect a write to the communications register. writing to the communications register selects the acquisition chan- nel, read/write operation for the next register, power- down/normal mode, and the address of the following register to be accessed. the max1415/max1416 have six user-accessible registers, which control the function of the device and allow the result to be read. write to the communications register before accessing any other registers. writing to the clock and setup registers after configuring and initializing the host processor serial port sets up the max1415/max1416. use self- or system calibrations to minimize offset and gain errors (see the calibration sec- tion for more details). set fsync = 0 to begin calibration or conversion. the max1415/max1416 perform free-run- ning acquisitions when fsync is low (see the using fsync section). the ? can poll the drdy bit of the communications register and read the data register when the drdy bit returns a 0. for hardware polling, the drdy output goes low when the new data is valid in the data register. the data register can be read multiple times while the next conversion takes place. the flow diagram in figure 11 shows an example sequence required to perform a conversion on channel 1 (ain1+/ain1-) after a power-on reset. output data rate f decimation rate clkin = 128 output data rate f decimation rate clkin . = 128 05 16-bit, low-power, 2-channel, sigma-delta adcs 28 ______________________________________________________________________________________ table 14. filter select and decimation rate clk fs1 fs0 decimation rate 0 0 0 391 0 0 1 313 010 78 011 39 1 0 0 384 1 0 1 320 110 77 111 38 max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 29 poll drdy output power-on reset initialize c/ p serial port write to the setup register. set self-calibration mode, gain to 0, unipolar mode, unbuffered mode. begin self-calibration/conversion by clearing fsync. (0x44) write to the communications register. set next operation as a write to the setup register. (0x10) write to the clock register. enable internal clock. set clock frequency to 2.4576mhz. select output update rate of 60hz. (0xa5) write to the communications register. select channel 1 and set next operation as a write to the clock register (0x20) write to the communications register. set next operation as a read from the data register. (0x38) read the data register (16 bits) write to communications register. set next operation as a read from the communications register. (0x08) read the communications register (8 bits) hardware polling software polling 0 (data ready) 0 (data ready) 1 (data not ready) 1 (data not ready) poll drdy bit figure 11. sample flow diagram for data conversion max1415/max1416 using fsync when fsync = 1, the digital filter and analog modula- tor are in a reset state, inhibiting normal operation. set fsync = 0 to begin calibration or conversion. when configured for normal operation (md1 and md0 set to 0), drdy goes low 3 x 1/output data rate after fsync goes low to indicate that the new conversion result is ready to be read from the data register. drdy returns high when a read operation on the data register is complete. as long as fsync remains low, the max1415/max1416 perform free-running conversions with the data registers updating at the output data rate. if the valid data is not read before the next conversion result is ready, drdy returns high for 500 x 1/f clkin before going low again to indicate a new conversion. set fsync = 1 to stop converting data. if fsync goes high while drdy is low (indicating that valid data has not yet been read from the data regis- ter), drdy does not reset high. drdy remains low until the new data is read from the data register or until fsync goes low to begin a new conversion. table 15 provides the duration-to-mode bits and dura- tion to drdy for each calibration sequence. duration-to- mode bits provide the time required for the calibration sequence to complete (md1 and md0 return to 0). duration to drdy provides the time until the first conver- sion result is valid in the data register ( drdy goes low). the pipeline delay necessary to ensure that the first conversion result is valid is t p (t p = 2000 x 1/f clkin ). when selecting self-calibration (md1 = 0, md0 = 1), drdy goes low 9 x 1/output data rate + t p after fsync goes low (or after a write operation to the setup register with md1 = 0 and md0 = 1 is performed while fsync is already low) to indicate new data in the data register. when zero-scale or full-scale calibration is selected, drdy goes low 4 x 1/output data rate + t p after fsync goes low (or while the zero-scale or full-scale calibra- tion command is issued when fsync is already low) to indicate new data in the data register (see the calibration section). calibration to compensate for errors introduced by temperature variations or system dc offsets, perform an on-chip cal- ibration. select calibration options by writing to the md1 and md0 bits in the setup register (table 9). calibration removes gain and offset errors from the device and/or the system. recalibrate with changes in ambient temperature, supply voltage, bipolar/unipolar mode, buffered/unbuffered mode, pga gain, and out- put data rate. the max1415/max1416 offer two calibration modes, self-calibration and system calibration. the channels of the max1415/max1416 are independently calibrated (see table 8). the calibration coefficients resulting from a calibration sequence on a selected channel are stored in the corresponding offset and gain register pair. self- and system calibration automatically calculate the offset and gain coefficients, which are written to the off- set and gain registers. these offset and gain coeffi- cients provide offset and gain error correction for the specified channel. self-calibration self-calibration compensates for offset and gain errors internal to the adc. prior to calibration, set the pga gain, unipolar/bipolar mode, buffered/unbuffered mode, and input channel setting. during self-calibration, ain+ and ain- of the selected channel are internally shorted together. the adc calibrates this condition as the zero- scale output level. for bipolar mode, this zero-scale point is the midscale of the bipolar transfer function. 16-bit, low-power, 2-channel, sigma-delta adcs 30 ______________________________________________________________________________________ table 15. calibration sequences calibration type (md1, md0) calibration sequence duration-to-mode bits* duration to drdy ** self-calibration (0,1) internal zero-scale calibration at selected gain plus internal full- scale calibration at selected gain 6 x 1/output data rate 9 x 1/output data rate + t p zero-scale system calibration (1,0) zero-scale calibration on ain at selected gain 3 x 1/output data rate 4 x 1/output data rate + t p full-scale system calibration (1,1) full-scale calibration on ain at selected gain 3 x 1/output data rate 4 x 1/output data rate + t p * duration-to-mode bits represents the completion of the calibration sequence. ** duration to drdy represents the time at which a new conversion result is available in the data register. next, an internally generated voltage (v ref /gain) is applied across ain+ and ain-. this condition results in the full-scale calibration. start self-calibration by setting md1 = 0, md0 = 1, and fsync = 0 in the setup register. self-calibration com- pletes in 6 x 1/output data rate. the md1 and md0 bits both return to 0 at the end of calibration. the device returns to normal acquisition mode and performs a con- version, which completes in 3 x 1/output data rate after the self-calibration sequence. the drdy output goes high at the start of calibration and falls low when the calibration is complete and the next conversion result is valid in the data register. the total time for self-calibration and one conversion (time until drdy goes low) is 9 x 1/output data rate. if drdy is low before or goes low during the calibration com- mand write to the setup register, drdy takes up to one additional modulator cycle (128/f clkin ) to return high to indicate a calibration or conversion in progress. system calibration system calibration compensates for offset and gain errors for the entire analog signal path including the adc, signal conditioning, and signal source. system calibration is a two-step process and requires individ- ual zero-scale and full-scale calibrations on the select- ed channel at a specified pga gain. recalibration is recommended with changes in ambient temperature, supply voltage, buffered/unbuffered mode, bipolar/ unipolar mode, pga gain, and output data rate. set the zero-scale reference point across ain+ and ain-. start the zero-scale calibration by setting md1 = 1, md0 = 0, and fsync = 0 in the setup register. when zero- scale calibration is complete (3 x 1/output data rate), md1 and md0 both return to 0. drdy goes high at the start of the zero-scale system calibration and returns low when there is a valid word in the data register (4 x 1/out- put data rate). the time until drdy goes low is com- prised of one zero-scale calibration sequence (3 x 1/output data rate) and one conversion on the ain volt- age (1 x 1/output data rate). if drdy is low before or goes low during the calibration command write to the setup register, drdy takes up to one additional modula- tor cycle (128/f clkin ) to return high to indicate a calibra- tion or conversion in progress. after performing a zero-scale calibration, connect the analog inputs to the full-scale voltage level (v ref /gain). perform a full-scale calibration by setting md1 = 1 and md0 = 1. after 3 x 1/output data rate, md1 and md0 both return to 0 at the completion of full- scale calibration. drdy goes high at the beginning of calibration and returns low after calibration is complete and new data is in the data register (4 x 1/output data rate). the time until drdy goes low is comprised of one full-scale calibration sequence (3 x 1/output data rate) and one conversion on the ain voltage (1 x 1/out- put data rate). if drdy is low before or goes low during the calibration command write to the setup register, drdy takes up to one additional modulator cycle (128/f clkin ) to return high to indicate a calibration or conversion in progress. in bipolar mode, the midpoint (zero scale) and positive full scale of the transfer function are used to calculate the calibration coefficients of the gain and offset registers. in unipolar mode, system calibration is performed using the two endpoints of the transfer function (figures 4 and 5). power-down modes the max1415/max1416 include a power-down mode to save power. select power-down mode by setting pd = 1 in the communications register. the pd bit does not affect the serial interface or the status of the drdy line. while in power-down mode, the max1415/max1416 retain the contents of all of its registers. placing the part in power-down mode reduces current consumption to 2? (typ) when in external cmos clock mode and with clkin connected to v dd or gnd. if drdy is high before the part enters power-down mode, then drdy remains high until the part returns to normal operation mode and new data is available in the data register. if drdy is low before the part enters power-down mode, indicating new data in the data register, the data register can be read during power-down mode. drdy goes high at the end of this read operation. if the new data remains unread, drdy stays low until the max1415/max1416 are taken out of power-down mode and resume data conversion. resume normal operation by setting pd = 0. the device begins a new conversion with a result appearing in 3 x 1/output data rate + t p , where t p = 2000 x 1/f clkin , after pd is set to 0. if the clock is stopped during power-down mode, allow sufficient time for the clock to startup before resuming conversion. if the external crystal/resonator is used and clkdis = 0, clkout remains active during power-down mode to provide a clock source for other devices in the system. if the internal oscillator is used, power-down mode shuts off the internal oscillator. max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 31 max1415/max1416 applications information applications examples strain-gauge measurement connect the differential inputs of the max1415/ max1416 to the bridge network of the strain gauge. in figure 12, the analog positive supply voltage powers the bridge network and the max1415/max1416 along with the reference voltage in a ratiometric configuration. the on-chip pga allows the max1415/max1416 to handle an analog input voltage range as low as 20mv to full scale. optical isolation for applications that require an optically isolated inter- face, see figure 13. with 6n136-type optocouplers, the maximum clock speed is 4mhz. the maximum clock speed is limited by the degree of mismatch between the individual optocouplers. faster optocouplers allow faster signaling at a higher cost. layout, grounding, and bypassing use pc boards with separate analog and digital ground planes. connect the two ground planes togeth- er at the max1415/max1416 gnd. isolate the digital supply from the analog with a low-value resistor (10 ? ) or ferrite bead when the analog and digital supplies come from the same source. ensure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. a 5ma current flowing through a pc board ground trace impedance of only 0.05 ? creates an error voltage of approximately 250?. layout the pc board to ensure digital and analog signal lines are kept separate. do not run digital lines (especial- ly the sclk and dout) parallel to any analog lines. if they must cross one another, do so at right angles. bypass v dd to the analog ground plane with a 0.1? capacitor in parallel with a 1? to 10? low-esr capac- itor. keep capacitor leads short for best supply-noise rejection. bypass ref+, ref-, and all analog inputs with a 0.1? capacitor to gnd. place all bypass capac- itors as close to the device as possible to achieve the best decoupling. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line is either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. inl for the max1415/max1416 is measured using the end- point method. this is the more conservative method. unipolar offset error for an ideal converter, the first transition occurs at 0.5 lsb above zero. offset error is the amount of deviation between the measured first transition point and the ideal point. bipolar zero error in bipolar mode, the ideal midscale transition occurs at ain+ - ain- = 0. bipolar zero error is the measured deviation from this ideal value. gain error with a full-scale analog input voltage applied to the adc (resulting in all ones in the digital code), gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function (with the offset error or bipolar zero error removed). gain error is usually expressed in lsb or a percent of full-scale range (%fsr). positive full-scale error for the ideal transfer curve, the code edge transition that causes a full-scale transition to occur is 1.5 lsb below full scale. the positive full-scale error is the dif- ference between this code transition of the ideal trans- 16-bit, low-power, 2-channel, sigma-delta adcs 32 ______________________________________________________________________________________ max1415 max1416 v dd clkin ref+ ref- ain1+ ain1- clkout cs sclk din dout drdy reset gnd v dd r ref active gauge dummy gauge 0.1 f 10 f 0.1 f 0.1 f r r 0.1 f 0.1 f figure 12. strain gauge measurement fer function and the actual measured value at this code transition. unlike gain error, unipolar offset error and bipolar zero error are included in the positive full-scale error measurement. bipolar negative full-scale error for the ideal transfer curve, the code edge transition that causes a negative full-scale transition to occur is 0.5 lsb above negative full scale. the negative full-scale error is the difference between the ideal value at this code transi- tion and the actual measured value at this code transition. input common-mode rejection input common-mode rejection is the ability of a device to reject a signal that is common to or applied to both input terminals. the common-mode signal can be either an ac or a dc signal or a combination of the two. cmr is often expressed in decibels. common-mode rejection ratio (cmrr) is the ratio of the differential sig- nal gain to the common-mode signal gain. power-supply rejection ratio power-supply rejection ratio (psrr) is the ratio of the input signal change (v) to the change in the converter output (v). it is typically measured in decibels. max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 33 max1415 max1416 din v cc 6n136 2k ? 100 ? sclk dout cs mosi sck miso iso 3v/5v v cc 6n136 2k ? 100 ? v cc 6n136 2k ? 100 ? +v cc v dd figure 13. optically isolated interface ordering information (continued) part temp range pin- package v dd ( v ) pkg code max1416 ene* -45? to +85? 16 pdip 5 p16-1 max1416ewe* -45? to +85? 16 wide so 5 w16-1 max1416eue -45? to +85? 16 tssop 5 u16-1 max1416aene* -45? to +85? 16 pdip 5 p16-1 max1416aewe* -45? to +85? 16 wide so 5 w16-1 max1416aeue* -45? to +85? 16 tssop 5 u16-1 MAX1416CNE* 0? to +70? 16 pdip 5 p16-1 max1416cwe* 0? to +70? 16 wide so 5 w16-1 max1416cue* 0? to +70? 16 tssop 5 u16-1 * future product? ontact factory for availability. chip information transistor count: 42,000 process: bicmos max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs 34 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) pdipn.eps max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs ______________________________________________________________________________________ 35 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) soicw.eps package outline, .300" soic 1 1 21-0042 b rev. document control no. approval proprietary information title: top view front view max 0.012 0.104 0.019 0.299 0.013 inches 0.291 0.009 e c dim 0.014 0.004 b a1 min 0.093 a 0.23 7.40 7.60 0.32 millimeters 0.10 0.35 2.35 min 0.49 0.30 max 2.65 0.050 0.016 l 0.40 1.27 0.512 0.496 d d min dim d inches max 12.60 13.00 millimeters min max 20 ac 0.447 0.463 ab 11.75 11.35 18 0.398 0.413 aa 10.50 10.10 16 n ms013 side view h 0.419 0.394 10.00 10.65 e 0.050 1.27 d 0.614 0.598 15.20 24 15.60 ad d 0.713 0.697 17.70 28 18.10 ae h e n d a1 b e a 0 -8 c l 1 variations: max1415/max1416 16-bit, low-power, 2-channel, sigma-delta adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. tssop4.40mm.eps package outline, tssop 4.40mm body 21-0066 1 1 g package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) |
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